1. Field of the Invention
One disclosed aspect of the embodiments relates to a switching power source device based on a synchronous rectification method.
2. Description of the Related Art
As an example of a conventional switching power source, a configuration using a comparator illustrated in FIG. 10 is known. The switching power source illustrated in FIG. 10 detects voltages at both ends of a switching element field effect transistor (FET) for synchronous rectification by using the comparator to drive the FET. In FIG. 10, the switching power source includes a transformer 1001, a DC power source 1002, an FET 1003 on a primary side (metal-oxide semiconductor FET: MOSFET), an electrolytic capacitor 1004 on a secondary side, a load 1005, a circuit 1006 for controlling a switching operation, an FET 1007 for synchronous rectification, and a comparator 1008.
After the FET 1003 on the primary side is turned ON to store energy in the transformer 1001, when the FET 1003 is turned OFF, a source voltage of the FET 1007 for synchronous rectification rises, causing a voltage of a + terminal of the comparator 1008 to be higher than that of a − terminal. Accordingly, the FET 1007 for synchronous rectification is turned ON. Then, current flows to be 0 ampere (A). When the current starts to flow from the + terminal of the capacitor 1004 through the transformer 1001, a voltage at the − input terminal of the FET 1007 for synchronous rectification becomes higher than that at the + input terminal. Then, a gate voltage of the FET 1007 for synchronous rectification drops to turn OFF the FET 1007 for synchronous rectification.
Such a configuration and an operation enable control of the FET for synchronous rectification with a small number of components. FIG. 11 illustrates, as a similar circuit configuration, an example where a comparator includes a discrete circuit having a PNP transistor and a NPN transistor. Even in the circuit illustrated in FIG. 11, an operation similar to that illustrated in FIG. 10 may be performed.
As the synchronous rectification method, there is also a method that does not directly detect a current. As an example of such a method, use of ET products of transformers is discussed in Japanese Patent Nos. 4158054 and 4210868. FIG. 12 illustrates such an example of a synchronous rectification circuit. In FIG. 12, the synchronous rectification circuit includes a transformer 1201, a power source 1202, an FET 1203 on a primary side, an FET 1204 for synchronous rectification, an electrolytic capacitor 1205 on a secondary side, a load 1206, a first constant current source 1207, a capacitor 1208, a second constant current source 1209, a reference voltage 1210, a comparator 1211, resistances 1212 and 1213, a voltage detection circuit 1214, and a constant voltage source 1215.
The first constant current source 1207 generates current proportional to a voltage of the transformer 1201 during an ON-period of the FET 1203 on the primary side, and stores a time product (integrated value of the voltage during the ON-period) of the voltage generated at the transformer 1201 as a voltage of the capacitor during the ON-period of the FET 1203 on the primary side. The second constant current source 1209 generates current proportional to a voltage generated during an OFF-period of the FET 1203 on the primary side, and is turned ON to discharge the voltage in the capacitor 1208 when the FET 1203 on the primary side is turned OFF. When the voltage of the capacitor 1208 drops to a predetermined value set based on the reference voltage 1210, the comparator 1211 operates to reverse a logical circuit, and the FET 1204 for synchronous rectification is turned OFF.
As other methods, there are a method where the configuration illustrated in FIG. 10 further includes a reference voltage source disposed in series to the input terminal of the comparator, and a method where a plurality of reference voltages is set as a threshold value, and hysteresis characteristics are given to prevent erroneous operations.
However, in the above configuration of the conventional switching power source illustrated in FIG. 10, in the case of an element where ON-resistance of the FET for synchronous rectification is low and a voltage between a drain and a source thereof is low, a problem of an incorrect operation occurs.
Especially, during light-load running (also referred to as critical mode or discontinuous mode) of the switching power source, the current flowing through the FET for synchronous rectification roughly drops to 0 A. In other words, since the voltage between the drain and the source of the FET for synchronous rectification also drops to about 0 A, when the element of low ON-resistance is used as the FET for synchronous rectification, it is difficult to detect the current. This problem may be solved by using an element of high ON-resistance. However, when the element of a high ON-resistance is employed, efficiency during a synchronous rectification operation is reduced.
On the other hand, the methods discussed in Japanese Patent Nos. 4158054 and 4210868, which do not directly detect the current, do not depend on ON-resistance of the FET. These methods are advantageous in that erroneous operations are limited because of the voltage integration, and a circuit configuration is simple. However, it is difficult to set a threshold value for determining timing to match OFF-timing of the FET for synchronous rectification with 0 A. It is because in setting the threshold value, when output voltage fluctuation or load fluctuation is large, for example, at the time of turning ON power, an average value that is a center value of charging and discharging of the capacitor fluctuates, and thus the OFF-timing of the FET for synchronous rectification may not match the timing of the current 0 A.
In the case of the methods discussed in Japanese Patent Nos. 4158054 and 4210868, since no current is directly detected, the circuit operates based on prediction and presumption. Accordingly, the FET for synchronous rectification must be turned OFF early to provide a certain margin. When the FET for synchronous rectification is turned OFF providing the margin, a conduction period of a body diode of the FET for synchronous rectification is extended, which consequently reduces efficiency.